This paper mainly introduces a multi-channel analog signal acquisition method based on MPC5634. It automatically transfers data between RAM and enhanced queued analog-to-digital converter eQADC module through enhanced direct memory access (DMA), which can efficiently and accurately Complete the acquisition of the analog signal.
1 Enhanced Queue Analog-to-Digital Converter eQADC Module
1.1 Structure of the eQADC module
The MPC5634's eQADC module has two independently operable ADC conversion units (ADC0 and ADC1), 40 analog channels (expandable), 0~5V conversion range, and conversion accuracy of 8 bits, 10 bits, and 12 bits. Optional, with software and hardware triggering methods, sampling mode is single-shot mode and continuous mode, etc., ADC working clock can reach 15MHz. Rate and accuracy can meet the requirements of automotive controllers. Figure 1 shows the block diagram of the eQADC module, showing the main components of the eQADC module.
Figure 1 Block diagram of the eQADC module
1.2 Command Cache CFIFO Working Mechanism
The eQADC module has 6 command buffer CFIFOs. Each CFIFO has 4 depths. The CFIFO has a single scan and continuous scan mode. When configured in different scan modes, the CFIFO has different trigger mechanisms. When configured in single scan mode, the eQADC conversion command sequence stored in the queue is executed once each time. When set to continuous scan mode, as long as the queue is started, it can continue to run. The flow of data is shown in Figure 2.
Figure 2 data flow
1.3 eQADC Command Format
eQADC has two command formats: configuration command and conversion command. The configuration command is used to initialize the eQADC module, such as enabling the ADC module unit, setting the clock division factor, converting the rate factor, enabling the DMA request, etc. The conversion command is mainly used to set which channel to acquire and which ADC module unit to convert. The result of the conversion is placed in which of the 6 result buffers, whether the result of the acquisition is corrected, and so on.
2 Enhanced Memory Direct Access (DMA) Module
The DMA controller is a host on the bus that transfers data between on-chip resources (Flash, RAM, I/O peripherals, etc.) and off-chip resources. The DMA has 32 channels, and only one channel at a time becomes the host on the bus and transmits data. To resolve conflicts between them, DMA has two programmable priority mechanisms: a fixed priority mechanism and a polling priority mechanism. Once a channel becomes the master, the channel transfers data from one memory address to another through a read-and-write operation. Each DMA channel has an independent Transmit Control Descriptor (TDCn).
3 multi-channel eQADC sampling program design
In this design, the data is transferred via DMA. Multi-channel eQADC sampling program design mainly includes command queue, result queue definition, eQADC initialization, DMA initialization, trigger CFIFO and so on. The design flow of the program is shown in Figure 3.
Figure 3 program flow
3.1 Defining an array
In this paper cQUEUE0[40] is defined as the storage array of the conversion command, and rQUEUE0[40] is defined as the storage array of the conversion result. The conversion commands for all channels are placed in the array cQUEUE0[40], and the final acquisition results are placed in the array rQUEUE0[40], which can be used by the car controller to read the data in rQUEUE0[40] at any time.
3.2 Initializing DMA
TCD0 corresponds to CFIFO0, and TCD1 corresponds to RFIFO0. Since this design can satisfy the design requirements as long as one command buffer CFIFO0 and one result buffer RFIFO0, only one CFIFO0, one RFIFO0, and their corresponding TCD0 and TCD1 are set. TCD0 is set. The source address is &cQUEUE0, the destination address is 0xFFF80010, the source address offset is 4, the transmission size is 32 bits, the secondary byte transmission number is NBYTES is 2, the main iteration number is 40, and the TCD1: source address is &rQUEUE0. The address is 0xFFF80032, the source address offset is 4, the transmission size is 16 bits, the secondary byte transmission number NBYTES is 2, and the main iteration number is 40.
3.3 Initializing eQADC
Initialize the conversion command storage array cQUEUE0[40]. This design uses the ADC0 module unit, 12-bit precision, and uses calibration to acquire 40 channels of analog at a time. Configure the register of the eQADC with a clock division factor of 2, enable DMA0, DMA1 request, and so on.
3.4 Correction Register Settings
The chip function of this project is very powerful. The previous calibration requires external hardware to correct the sampling result. The MPC5634 has its own calibration function. The calibration used in this project is as follows: the initial conversion result of the ADC will be corrected by the MAC unit. . The MAC unit performs the following algorithms to correct:
Idealresult=GCCXADCresult+OCC+2 (1)
GCC is the constant for gain correction, which is defined in register ADCn_GCCR; OCC is the offset correction constant, which is defined in register ADCn_OCCR.
The values ​​of GCCR and OCCR are determined by calculations. Solve by the following formula:
Idealresult1=GCCXADCresult1+OCC+2 (2)
Idealresult1=GCCXADCresult1+OCC+2 (3)
In order to find the values ​​of GCCR and OCCR, we only need the ideal result and the actual result of the two channels. The voltage values ​​of channel 44 and channel 43 correspond to 0.25Vdd and 0.5Vdd, respectively, and their actual results can be collected. Therefore, the values ​​of GCCR and OCCR can be found.
3.5 Enabling DMA Requests
Set enable DMA0 and DMA1 requests.
3.6 Trigger CFIFO0
Set CFIFO0 to continuous conversion mode, so that the signal can be continuously and continuously collected, and the collected result is put into the result storage array in time, so that the data read by the car controller in the result storage array is up-to-date. The results of the acquisition allow the controller to control individual actuators based on the latest data.
4 main program and execution results
Void main(void)
{
Uint32_t cQUEUE0[40]; //Define the command storage array
Uint16_t rQUEUE0[40]; //Result store array
Dma_init_fnc(); //DMA initialization
Eqadc_init_fnc (); //eQADC initialization
Set_calconstants (); / / correction register settings
Dma_able();//Enable DMA0, DMA1
Cfifo0_trig();//Enable DMA0, DMA1
While(1)
{
}
}
5 Conclusion
This design completes the design of the sampling module of the automotive controller, which guarantees the requirements of the vehicle controller in terms of time and accuracy. Through continuous testing, the design achieves the performance and functionality required by the system.
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