With the continuous advancement of power automation, the demand for precise time synchronization in power systems has become increasingly critical. Ensuring accurate time alignment is essential for maintaining the reliability and efficiency of power generation and distribution. One of the most effective solutions to achieve this is through the use of the GPS global satellite positioning system, which provides highly accurate time synchronization. As a result, major power companies, including the State Power Corporation and provincial grid operators, have placed significant emphasis on implementing time-synchronization systems. These organizations mandate that all power production and operational devices utilize satellite-based timekeeping to ensure consistency and accuracy.
Currently, GPS receivers typically output standard time information using the IRIG-B (DC) time code format. This format is widely used in power systems due to its precision and reliability. In response to this, this paper presents an IRIG-B (DC) time code decoding design based on FPGA technology, aiming to enhance the performance and flexibility of time synchronization in power systems.
**Introduction to IRIG-B Code**
The IRIG-B (DC) time code, commonly referred to as the B code, is a serial time code developed by the IRIG (Instrumentation Research Group) for timing applications. It operates with a frame length of 1 second and contains 100 symbols. The B code uses pulse width modulation to encode data, with three distinct pulse widths representing "0", "1", and a flag bit "P". Specifically, "0" corresponds to a 2 ms pulse, "1" to a 5 ms pulse, and "P" to an 8 ms pulse. Each symbol lasts for 10 ms, making the B code a reliable and structured method for time transmission.
A full frame of the B code begins with two consecutive "P" pulses. The first "P" is labeled P0, and the second is PR. The rising edge of PR marks the start of the second represented by the current frame. If PR is at position 0, then each symbol within the frame is numbered from 0 to 99. The flag bits P1 through P9 are located at positions 9, 19, 29, ..., 99, respectively. The B code includes detailed time information such as seconds, minutes, hours, days, and the Time of Day (TOD), allowing for precise time tracking.
The second information is divided into "seconds" and "tens," represented by BCD codes ranging from 00 to 59. The "seconds" portion uses symbols 1–4, while "tens" use symbols 6–8. Similarly, the minute information is split into "minutes" and "tens," with "minutes" using symbols 10–13 and "tens" using symbols 15–17. The hour information is divided into "hours" and "tens," with "hours" occupying symbols 20–23 and "tens" using symbols 25–26. Days are represented as the total number of days since January 1st, ranging from 1 to 365 (or 366 in leap years). The TOD information spans 17 symbols, providing the exact number of seconds from the start of the day.
**FPGA Decoding Scheme**
Field-Programmable Gate Arrays (FPGAs) are highly versatile integrated circuits used for designing complex digital systems. They allow for reconfigurable logic and are ideal for real-time signal processing tasks. In this project, the Xilinx Spartan-3 series XC3S1500 chip is employed. This device features 29,952 logic cells and 1.5 million gates, along with 333 I/O pins, making it suitable for high-performance applications. The chip supports online programming and is available in an FG456 package.
Xilinx's ISE software is used for FPGA development, supporting both schematic and VHDL-based design methods. The ISE 10.1 version is utilized in this project to facilitate the design process. After completing the design input and compilation, simulation is necessary to verify functionality. ModelSim SE 6.6e is used for simulation, offering a robust and efficient environment for debugging and testing.
The project utilizes VHDL and a top-down design methodology to implement hierarchical management. To ensure stability and reliability, a fully synchronous design is adopted, where all state changes occur on the rising edge of the clock signal. This approach minimizes potential timing issues and enhances overall system performance.
**Global Control Module**
The global control module plays a central role in managing the timing and synchronization of the entire system. It generates global control signals and oversees other modules. First, the input 10 MHz frequency is multiplied to 50 MHz, enabling the system to operate at a higher speed. Then, the rising edge of the B (DC) code symbol is detected, and the global control signal count is reset at this point. Once reset, the counter starts counting under the control of the 50 MHz clock.
The lower 17 bits of the count serve as a 2.2 ms timer, while the 17th and 18th bits are used to mark the sampling points of the B code symbols, ranging from 0 to 3. The 19th to 25th bits track the symbol index, ranging from 0 to 99. Finally, the module searches for the frame header by analyzing the output of the B code sampling module. When two consecutive "P" flags (P0 and PR) are detected, the frame header is identified, and the BCH decoding process begins. Otherwise, the search continues, and the control signal count is reset.
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