With the continuous advancement of power automation, the demand for precise time synchronization between power systems and time has become increasingly critical. As the accuracy requirements for time synchronization grow, the use of GPS-based time synchronization has emerged as the most effective solution to enhance the level of power production and management automation while ensuring operational reliability. Major power companies, including the State Power Corporation and provincial grid operators, have placed significant emphasis on the development of time-synchronization systems for power networks, mandating that all devices in power generation and operation must use satellite clocks for accurate timekeeping.
Currently, GPS receivers typically output standard time information using the IRIG-B (DC) time code format. To meet the growing need for accurate and reliable time synchronization, this paper presents a design for an IRIG-B (DC) time code decoding system based on FPGA technology. This approach ensures efficient and precise decoding of time codes, making it ideal for applications in power systems where timing accuracy is essential.
**Introduction to IRIG-B Code**
The IRIG-B (DC) time code, commonly referred to as the B code, is a serial time code developed by the IRIG (Instrumentation Research Group) for use in various applications requiring high-precision time synchronization. The B code is structured into 100 symbols per second, with each symbol lasting 10 milliseconds. It uses pulse width modulation to represent binary data, with three distinct pulse widths: 2 ms for '0', 5 ms for '1', and 8 ms for the flag bit 'P'. These symbols are used to encode time information such as seconds, minutes, hours, days, and the Time of Day (TOD).
Each frame of the B code begins with two consecutive 'P' bits, with the first being P0 and the second PR. The rising edge of PR marks the start of the second represented by the current frame. The positions of the flag bits P1 through P9 are at symbols 9, 19, 29, ..., 99 respectively. The B code contains detailed time information, including seconds, minutes, hours, days, and TOD, which is crucial for maintaining accurate time synchronization across power systems.
**FPGA Decoding Scheme**
Field Programmable Gate Arrays (FPGAs) are widely used in digital circuit design due to their flexibility and reprogrammability. In this project, the Xilinx Spartan3 series XC3S1500 chip was selected for its high performance and large logic capacity. With 29,952 logic units and 1.5 million gates, the XC3S1500 provides sufficient resources for implementing complex decoding algorithms.
The design was developed using Xilinx ISE 10.1 software, which supports both schematic entry and VHDL text-based design. After completing the design input and compilation, simulation using ModelSim SE 6.6e was performed to verify the functionality of the system. The design follows a top-down approach, using VHDL to implement hierarchical modules and ensure stability and reliability.
A key component of the design is the global control module, which manages timing and coordinates the decoding process. It generates a 50 MHz clock signal from a 10 MHz input, ensuring precise timing throughout the system. The module also detects the rising edge of the B code symbols, resets the counter, and initiates the decoding process. Once the frame header is detected, the system proceeds with BCH decoding to extract the time information accurately.
This FPGA-based IRIG-B (DC) decoding system offers a robust and efficient solution for time synchronization in power systems, meeting the increasing demands for precision and reliability in modern power infrastructure.
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